Filed and public-safe areas
Patent Portfolio
Board Design Reliability Analysis Checklist Guidelines
U.S. Patent Application No. 18/311,244
Structured engineering methods for board-level reliability analysis across component selection, circuit design, placement, layout, and manufacturing review.
Profile-Based Ethernet Connectivity for Multi-Lane SoC Devices
U.S. Patent Application No. 19/433,978
Governed connectivity profiles for complex multi-lane SoC environments and repeatable interconnect behavior.
Graph-Based Multi-Tier Semiconductor Supply-Chain Risk Scoring and Closed-Loop Mitigation
U.S. Patent Application No. 19/535,459
Graph-based visibility and decision support for multi-tier sourcing risk, provenance, and mitigation priorities.
Closed-Loop Manufacturing Stability Systems and Methods for Multi-Domain Control Production
U.S. Patent Application No. 19/534,285
Distributed control and manufacturing stability logic for detecting excursions and preserving throughput and trust.
AI-Certified Lithography Control
Pre-filing invention | public-safe summary only
High-level positioning around traceable confidence, bounded corrective action, and certifiable process-window control.